1. Field of the Invention
The present invention relates to a liquid crystal display apparatus, and more particularly to a liquid crystal display apparatus with a built-in peripheral circuit in which driving units and a display unit are formed on a substrate.
2. Description of the Related Art
As a driving system for driving a small-sized and high-resolution liquid crystal display panel, there has been employed a method of using thin film transistors to form a matrix peripheral circuit on a glass substrate. This method has been reported in, for example, xe2x80x9cSID International Symposium Digest of Technical Papersxe2x80x9d, pp. 879-882, 1998. Also, concerning the details of the active matrix driving system and the liquid crystal display module, the detailed explanation is given in Syouichi Matumoto as editor and writer, entitled xe2x80x9cLiquid Crystal Display Technologyxe2x80x9d (Sangyo Tosho).
Hereinafter, the explanation will be given below concerning the configuration of a liquid crystal display apparatus illustrated in FIG. 2 and the schematic configuration of a liquid crystal display apparatus according to the present invention illustrated in FIG. 1. This is intended in order to clarify the difference between the related art and the present invention.
In FIG. 1, display image data and synchronization signals are supplied from input terminals 214 of a liquid crystal display module 105 to a digital data driver unit 106 through high-speed data buses 203 and high-speed control buses 216. In the digital data driver unit, low-speed data buses 102 and low-speed control buses 107 are arranged in such a manner that they are separated for each of a plurality of blocks 103. The display image data on the low-speed data buses are present in parallel and are then transferred to data latches by the low-speed data buses at a transfer rate lower than that of the high-speed data buses. Here, the parallel distribution is executed by high-speed data rearranging circuits 101 located for the respective blocks. Also, synchronization signals necessary for shift registers and the data transfer are generated individually for each block by high-speed data control circuits 104 arranged on each block. The distributing operations of the display data into the data latches are thereby performed with timings that are independent for the respective blocks.
In the configuration of the TFT liquid crystal display module illustrated in FIG. 2, there are included none of the low-speed data buses that transfer the display data at the lower rate. Instead, one set of high-speed data buses 203, which have been inputted into a liquid crystal display module 215 from input terminals 214, and high-speed control buses 216 drive shift registers 202, thereby transferring the display image data to the respective data latches 204. After that, the display data by the amount of one line on the data latches are latched into line memories 205. Then, the digital display data, after being amplified in the voltage by level shifters 206, are converted into a liquid crystal driving voltage by D/A converting circuits 207 provided for each signal line. The liquid crystal driving voltage then drives a pixel unit 209 through signal line 208. A scan drive circuit 213, which includes a shift register 211 connected to each other in series and a level shifter 212 outputs a scan line select pulse for the pixel unit to scan lines 210, thereby accomplishing the active matrix display. In this system, as the display panel grows large-sized and obtains a higher resolution, it becomes required to increase the wiring width in order to suppress signal delays occurring in the data buses. This has become a cause of increasing an area of the wiring unit.
Also, it is required to drive the data latches and the line memories in the data driver circuit on condition that all of them are in synchronization with each other. On account of this, if differences in time increase among the synchronization signals toward the respective units of the circuit, it becomes impossible to synchronize the respective units of the circuit. This situation has made it difficult to implement the peripheral circuit on the large-sized display panel with the use of the TFTs of comparatively drivability.
Also, since a number of data latches are connected to one set of the data buses, the capacitance value of a data bus wiring becomes larger. On account of this, a time constant determined by the wiring resistance and the wiring capacitance increases, eventually prolonging the wiring delay time. This condition has also made it difficult to implement the peripheral circuit on the large-sized display panel.
As described above, toward the liquid crystal display module for each horizontal scanning time-period, it is required to transfer, through the data buses within the panel, the pixel display data by the amount of one scanning line to the respective data latches corresponding to the signal wirings of the pixel unit. The data transfer rate at this time is increased as the number of the pixels becomes larger. For example, in the configuration of 1024xc3x97768 pixels, it is necessary to achieve a high-speed data transfer in which 18-bit data for each pixel are transferred with a frequency of about 50 MHz.
In order to execute such a high-speed data transfer, the display data of one field are rearranged for each pixel in series one after another, then being supplied through the data buses connected to all the data latches. After that, the data are transferred by operating a specified data latch in accordance with a start pulse, a transfer clock signal, and data latch signals, that are shifted in sequence using the shift register circuits. However, the data buses necessitate a length of the display region in the horizontal direction, and have a long wiring length. What is more, the large numbers of data latches accompanied by the capacitance load are connected to a single wiring. Thus, the load capacitance of the wiring is built up with the number of the pixels in the panel, thereby increasing the wiring delay. Namely, increasing the number of the pixels requires the data transmission at an even higher transfer rate; nevertheless, the wiring resistance and the wiring load capacitance also increase and thus the wiring delay is prolonged as well. Consequently, in the above-described configuration, it was difficult to upsize the high-resolution display panel.
It is an object of the present invention to provide a liquid crystal display apparatus that has only a small load capacitance on the display panel and that, even in the large-sized high-resolution panel, permits the display data inputted into the high-speed data buses to be transmitted up to terminal ends of the data buses with a small waveform distortion.
In order to accomplish the above-described object of the present invention, a display region using the TFT (thin film transistors) active matrix system and a peripheral circuit using the TFTs are formed on a substrate of the liquid crystal display panel of the liquid crystal display apparatus. Moreover, there are provided high-speed buses which include high-speed data buses and high-speed control buses, and low-speed data buses divided into the blocks, and a signal wiring driving circuit. The high-speed buses supply high-speed display data from the outside. A waveform shaping circuit provided in the course of bus wirings corrects the waveform distortion due to the signal delay in the bus wirings. In addition, the high-speed buses transfer to terminal ends the high-speed display data and high-speed control signals such as dot clock and synchronization signals.
The display data are distributed in parallel onto the large numbers of low-speed data buses for each block, then being transferred in sequence to the respective data latches. After that, the digital display data are converted into the liquid crystal driving voltage by respective line memories and respective D/A converting circuits so as to drive an active matrix display unit.
Also, the low-speed data buses are divided into the blocks and are caused to operate by individual timing signals. This makes it possible to fetch the display data, which have been distributed in parallel onto the large numbers of low-speed data buses, into the large numbers of data latches in sequence at a low data transfer rate. Furthermore, even if a tremendous signal delay occurs between the blocks on the high-speed data transfer buses, it is possible to correctly transfer the display data to the respective latches because the sampling operations toward the latches are independent for the respective blocks. The above-described effects permit the display data to be transferred to the respective data latches even if the display data transfer rate is increased in the high-resolution large-sized panel. Consequently, it is possible to speed up, as a whole, the data transfer rate even in the case of the large-sized panel.
A feature of the configuration according to the present invention lies in a point of providing the low-speed data buses that are independent for each block, so that the synchronization controls are made independent for each block.
First, the display image data is input to the liquid crystal display module, and supplied on the high-speed data buses. The display image data that the high-speed data control circuits cause to correspond to each block are rearranged in parallel by the high-speed data rearranging circuits onto the low-speed data buses, the number of which is larger than that of the high-speed data buses. The data latch circuits connected to the high-speed data buses are at the capacitance load. Accordingly, if this capacitance load is built up, the wiring delay increases, thus making it difficult to speed up the data transfer. The large numbers of data latch circuits that are equivalent to the number of the signal lines have been connected to the high-speed data buses. In the configuration according to the present invention, however, a single data latch circuit is connected to the high-speed data buses for each block. Furthermore, while data in no correspondence with a block is being transferred, the low-speed data buses can be cut off from the high-speed data buses. This makes it possible to exceedingly reduce the capacitance load of the data bus wiring. Similarly, regarding the high-speed control buses as well, the large numbers of shift registers have been connected to the high-speed control buses in the configuration. In the present invention, however, only a single high-speed data control circuit is connected to the high-speed control buses for each block. This makes it possible to reduce the capacitance load. In this way, it is possible to drive the high-speed buses with a low capacitance load. This condition permits the high-speed data bus wirings to be implemented using a fine wiring, thereby bringing about an advantage of making the circuit area smaller.
Next, the present invention exhibits a feature that the data is transferred from the low-speed data buses to the data latches in accordance with the individual synchronization signal for each block. In the related art, all the shift registers and the data latches of an entire display panel have been driven in accordance with a high-speed synchronization signal such as a dot clock on a wiring that is common to the shift registers and the data latches. On account of this, if the waveform is distorted due to causes such as the wiring delay or there exists a significant shift in the phase between the data and the synchronization signal, it becomes impossible to perform the data latch operation over the entire data driver circuit. This situation, accordingly, has become a bottleneck in embodying the large-sized and high-resolution display panel. Meanwhile, according to the present invention, the synchronization signals necessary for the data latch operation are generated independently for each block. Consequently, even if a delay occurs on the high-speed data buses, the synchronization has been achieved within each block, thus allowing a secure data latch operation even in the case of the large-sized and high-resolution panel. Since the data transfer speed within a block is low, the data buses within each block are of the low-speed data buses. Thus, a time for the data latch operation can be prolonged as compared with the conventional configuration. This results in an advantage of allowing the data latch to be performed more securely. Owing to this, even if the transmission delay occurs to some extent in the high-speed control buses or the high-speed data buses, it is possible to perform the data latch operation. Consequently, it becomes possible to correct the waveform distortion during the wiring transmission by providing a waveform shaping circuit in the course of the high-speed data bus wirings, thereby allowing the data transfer even when a wiring length is long. This also results in an advantage of allowing the large-sized panel to be implemented easily.
Also, the data driver circuit is divided into the blocks so that the data latch operation and the D/A conversion operation can be executed individually. This condition averages the power to be consumed in the circuits in these blocks, thereby making it possible to lessen width of the power supply wiring. Accordingly, it becomes possible not only to lessen the area of the data driver circuit but also to lessen a peak output of a power supply circuit for driving the data driver circuit. This reduces the load of a power supply circuit, thus bringing about an advantage of allowing the large-sized panel to be driven easily.